Free sample   Digital electronics assignment qanda based on logic gates

## Digital Electronics Assignment: Q&A Based On Logic Gates

Question

Task:
Your digital electronics assignment should address the following questions:

Q.1 A clocked synchronous state machine using positive-edge-triggered D flip-flops.

1. Write the excitation equations for the two flip-flops D0 and D1.
2. Write the state equations and then tabulate the state table.
3. Write the output equations for output MAX.
4. Draw state diagram corresponding to the state machine of your state table.

Q.2 The internal structure of a commercial IC 74LS109 is shown below.

The input labelled PR (preset) operates on the falling edge of PR and hence shown as PR_L.

1. Explain the operation of this circuit using timing diagrams.
2. Explain the Master-Slave nature of this flip-flop. What is the function of the Preset (PR) input?
3. Corresponding to the timing waveforms shown here for J, K and CLK, draw output waveform for Q..

Q.3 In the figure below, the first stage is a 4-to-1 multiplexer and the second stage is a 2-to-1 multiplexer. A, C and D are inputs that control the functionality of this circuit.

Write Boolean equation that represents the functionality of this circuit. In other words, write the function of Y in terms of A, C and D. i.e., Y = f (A, C, D)

Q.4 Referring to sequential circuits, what is the difference between Synchronous and Asynchronous reset?

State advantages of i) synchronous and ii) asynchronous reset

State disadvantages of i) synchronous and ii) asynchronous reset

Q.5 Implement the following circuits:

1. 3 input NAND gate using minimum no of 2 input NAND Gates
2. 3 input NOR gate using minimum no of 2 input NOR Gates
3. 3 input XNOR gate using minimum no of 2 input XNOR Gates

Q.6 Compare the delays of a 32-bit ripple-carry adder and a 32-bit carry-lookahead adder which are built with 4-bit adder modules. Assume that each two-input gate has a delay of 100 ps (AND has 100 ps, OR gate has 100 ps and XOR gate has 100 ps). Each full adder in the ripple-carry adder has a delay of 300 ps. In the carry-lookahead adder, the 4-bit carrylookahead generator has 200ps delay.

Figure above shows a 32-bit Carry-lookahead adder built using 4-bit adder blocks.

Figure above is a 4-bit Carry-lookahead adder internal circuit.

Q.7 For the circuit diagram shown below, draw the output waveform precisely below the input waveform showing the time details to the resolution of 0.5ns. Note that the CLK period is 1ns. Input pulse starts at 1ns and ends at 5ns. You need to draw output to this resolution and scale and include that figure in your answer. Explain the reasoning you used in drawing the output waveform with sufficient details. What is the function performed by this circuit?

Q.8 Gray codes have a useful property in that consecutive numbers differ in only a single bit position. Table given below lists a 3-bit Gray code representing the numbers 0 to 7. Design a 3-bit modulo 8 Gray code counter Finite State Machine with no inputs and three outputs. (A modulo N counter counts from 0 to N ? 1, then repeats. For example, a watch uses a modulo 60 counter for the minutes and seconds that counts from 0 to 59.) When reset, the output should be 000. On each clock edge, the output should advance to the next Gray code. After reaching 100, it should repeat with 000.

Your answer should consist of 1) State diagram, 2) State transition table, 3) The Flip-Flop characteristic equations, 4) State equations and 5) Hardware implementation of the Finite State Machine using D-type Flip-Flops.

Q.9 A circuit has four inputs and two outputs. The inputs ?3:0 represent a number from 0 to 15. Output P should be TRUE if the number is prime (0 and 1 are not prime, but 2, 3, 5, and so on, are prime). Output D should be TRUE if the number is divisible by 3. Give simplified Boolean equations for each output and sketch a circuit.

Q.10 John will enjoy his picnic on sunny days that have no ants. He will also enjoy his picnic any day he sees a hummingbird, as well as on days where there are ants and ladybugs. Write a Boolean equation for his enjoyment (E) in terms of sun (S), ants (A), hummingbirds (H), and ladybugs (L).

Q.11 Anita needs to implement the function

to finish her digital project, but when she looks in her lab kit, the only part she has left is an 8:1 multiplexer. How does she implement the function using only the 8:1 multiplexer?

Q.12 Explain why a designer might choose to use a ripple-carry adder instead of a carry-look ahead adder.

Answer

Q1) A clocked synchronous state machine using positive-edge-triggered D flip-flops.

1. Write the excitation equations for the two flip-flops D0 and D1 within this digital electronics assignment.
• The following excitation equations are obtained by observation of the given circuit
2. Write the state equations and then tabulate the state table.
• We define the states as follows,

The state equations are given as,

From these equations, we can construct the following state table:

3. Write the output equations for output MAX.
• By observing the circuit we get,

4. Draw a state diagram corresponding to the state machine of your state table.
• We can draw the following state diagram according to our state table. The values on the arrows are Input/Output.

We can see that the output is high only for the transition from S3 to S0 when Q1, Q0 and I all are high.

Q2) The internal structure of a commercial IC 74LS109 is shown below.

The input labelled PR (preset) operates on the falling edge of PR and hence shown as PR_L.

1. Explain the operation of this circuit using timing diagrams.
• When the CLR_L switch is high (PR_L=low) it sets the output to 1 irrespective of the other inputs and when it is low, both Q and QN are high. When Preset is high and CLR is low, Q and QN remain at 0 and 1 respectively. When PR_L and CLR_L are both high, the circuit behaves like a JK flip flop but with different states. The truth table is as follows:

2. Explain the Master-Slave nature of this flip-flop. What is the function of the Preset(PR) input?
• The Master-Slave nature of this circuit is easily observed when the circuit is simulated. The first flip flop is the Master while the second is the Slave. On simulating this circuit, we can observe that the Master FF changes first and after a half clock cycle the Slave output follows. The Preset input is necessary to drive the Master FF or else the Master FF is stuck in race condition (both q and qn are high) due to which the Slave FF stays in the same state.

3. Corresponding to the timing waveforms shown here for J, K and CLK, draw output waveform for Q.
• From the truth table we can draw the resultant waveform of Q.

Q3) In the figure below, the first stage is a 4-to-1 multiplexer and the second stage is a 2-to-1 multiplexer. A, C and D are inputs that control the functionality of this circuit. Write a Boolean equation that represents the functionality of this circuit. In other words, write the function of Y in terms of A, C and D. i.e., Y = f (A, C, D).

• The function of Y is as follows,

Q4) Referring to sequential circuits, what is the difference between Synchronous and Asynchronous reset?

State advantages of i) synchronous and ii) asynchronous reset.

State disadvantages of i) synchronous and ii) asynchronous reset.

• A synchronous reset signal resets the flip-flop synchronously(i.e. on the active edge of the clock)

An asynchronous resets the flip flop without regard to the clock signal and the system is reset as soon as the flip flop receives the reset signal

• Advantages of:
1. Synchronous Reset:
• Completely Synchronous circuit
• Circuit is not affected by glitches
• Will always meet reset recovery time
2. Asynchronous Reset:
• Fast when compared to synchronous reset
• Reset has high priority
• No need of clock
• Disadvantages of:
1. Synchronous Reset:
• Reset signal needs to be wide enough to be seen at clock edge
• Not differentiable from other signals hence can lead to timing issues
• If clock is gated then synchronous reset cannot be used
• Slower than asynchronous reset
2. Asynchronous Reset:
• Problem at de-assertion. If pulse ends near the clock edge metastable output can occur.
• Spurious glitches can cause circuit to reset

Q5) Implement the following circuits:

1. 3 input NAND gate using minimum no of 2 input NAND Gates
• Output of the first NAND gate is (~A)+(~B). Giving the same input to a NAND gate gives us the negative input i.e. AB. Giving this as an input to the third NAND gate along with C gives us ~(ABC) which is the result of a 3-input NAND gate.

2. 3 input NOR gate using minimum no of 2 input NOR Gates
• Output of the first NOR gate is (~A)(~B). Giving the same input to a NOR gate gives us the negative input i.e. A+B. Giving this as an input to the third NOR gate along with C gives us ~(A+B+C) which is the result of a 3-input NOR gate.

3. 3 input XNOR gate using minimum no of 2 input XNOR Gates
• A 3-input XOR gate acts like an odd parity checker. Hence I have taken a 3-input XNOR gate to be an even parity checker. The output of first XNOR gate is ~(A?B). Passing that through the second XNOR gate along with C gives us ~(~(A?B)?C). Getting the XNOR of an input with 0 gives us the negative of it. Therefore the final output is ~(A?B)?C which gives high output when even number of inputs are high.

Q6) Compare the delays of a 32-bit ripple-carry adder and a 32-bit carry-lookahead adder which are built with 4-bit adder modules. Assume that each two-input gate has a delay of 100 ps (AND has 100 ps, OR gate has 100 ps and XOR gate has 100 ps). Each full adder in the ripple-carry adder has a delay of 300 ps. In the carry-lookahead adder, the 4-bit carry-lookahead generator has 200ps delay.

For a 32 bit RCA, there are 32 Full Adders in sequence therefore the total delay is the sum of all the delays.

For a 32 bit CLA, there are 8 4-bit carry generators in sequence with two XOR gates in between.

Hence we can calculate the total delay in both adders as,

The delay in RCA is 9600ps, three times the delay in CLA of 3200ps.

Q7) For the circuit diagram shown below, draw the output waveform precisely below the input waveform showing the time details to the resolution of 0.5ns. Note that the CLK period is 1ns. Input pulse starts at 1ns and ends at 5ns. You need to draw output to this resolution and scale and include that figure in your answer. Explain the reasoning you used in drawing the output waveform with sufficient details. What is the function performed by this circuit?

• The D-flip flop delays the input for one clock cycle. Therefore after passing through the D-flip flop the pulse was delayed by 1ns. As the output is the OR of I/P, Q1 and Q2 the result is that the pulse is extended in time for 2ns. The function of the circuit is to extend the input pulse by 2ns.

Q8) Gray codes have a useful property in that consecutive numbers differ in only a single bit position. Table given below lists a 3-bit Gray code representing the numbers 0 to 7. Design a 3-bit modulo 8 Gray code counter Finite State Machine with no inputs and three outputs. (A modulo N counter counts from 0 to N ? 1, then repeats. For example, a watch uses a modulo 60 counter for the minutes and seconds that counts from 0 to 59.) When reset, the output should be 000. On each clock edge, the output should advance to the next Gray code. After reaching 100, it should repeat with 000.

1. State diagram
• The states are S0:S7 which go from 000:111. The output is mentioned on the arrow.
2. State transition table
• From the above state diagram, we get the following state transition table

Where q2, q1, q0 are the outputs of the D-flip flops and q2q1q0 (000:111) corresponds to S0:S7. Q2, Q1, Q0 are the outputs of the FSM.

3. The Flip-Flop characteristic equations
• From analysing the state transition table, we find the following flip flop characteristic equations keeping in mind q2+ = D2, q1+ = D1 and q0+ = D0

4. State equations

5. Hardware implementation of the Finite State Machine using D-type Flip-Flops
• Using the flip flop characteristic equations, we can build the hardware for the gien circuit

Q9) A circuit has four inputs and two outputs. The inputs ? 3:0 represent a number from 0 to 15. Output P should be TRUE if the number is prime (0 and 1 are not prime, but 2, 3, 5, and so on, are prime). Output D should be TRUE if the number is divisible by 3. Give simplified Boolean equations for each output and sketch a circuit.

• From the truth table we have:

For P:

For D:

Q10) John will enjoy his picnic on sunny days that have no ants. He will also enjoy his picnic any day he sees a hummingbird, as well as on days where there are ants and ladybugs. Write a Boolean equation for his enjoyment (E) in terms of sun (S), ants (A), hummingbirds (H), and ladybugs (L).

• Enjoyment = [(Sunny)AND(No Ants)]OR(Hummingbirds)OR[(Ants)AND(Ladybugs)]

Q11) Anita needs to implement the function to finish her digital project, but when she looks in her lab kit, the only part she has left is an 8:1 multiplexer. How does she implement the function using only the 8:1 multiplexer?

• Using a truth table we can see that Y=1 for ABC={000, 011, 100, 101, 110}. Therefore the function can be implemented by setting ABC belonging to the above set to be HIGH and grounding the other inputs.

Q12) Explain why a designer might choose to use a ripple-carry adder instead of a carry-lookahead adder

• A designer may choose a Ripple Carry Adder(RCA) over Carry Lookahead Adder(CLA) if there are strict power dissipation constraints as the power dissipation of RCA is less than that of CLA.
• Another reason may be that the no. of bits to be added is less hence using RCA would be feasible as the complexity of RCA is less than that of CLA.

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